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| general description the max6715a?ax6729a/max6797a are ultra-low-volt- age microprocessor (?) supervisory circuits designed to monitor two or three system power-supply voltages. these devices assert a system reset if any monitored supply falls below its factory-trimmed or adjustable threshold and main- tain reset for a minimum timeout period after all supplies rise above their thresholds. the integrated dual/triple supervisory circuits significantly improve system reliability and reduce size compared to separate ics or discrete components. these devices monitor primary supply voltages (v cc 1) from 1.8v to 5.0v and secondary supply voltages (v cc 2) from 0.9v to 3.3v with factory-trimmed reset threshold voltage options (see the reset voltage threshold suffix guide ). an externally adjustable rstin input option allows customers to monitor a third supply voltage down to 0.62v. these devices are guaranteed to be in the cor- rect reset output logic state when either v cc 1 or v cc 2 remains greater than 0.8v. a variety of push-pull or open-drain reset outputs along with watchdog input, manual-reset input, and power-fail input/output features are available (see the selector guide ). select reset timeout periods from 1.1ms to 1120ms (min) (see the reset timeout period suffix guide ). the max6715a?ax6729a/max6797a are avail- able in small 5-, 6-, and 8-pin sot23 packages and oper- ate over the -40? to +125? temperature range. applications features v cc 1 (primary supply) reset threshold voltages from 1.58v to 4.63v v cc 2 (secondary supply) reset threshold voltages from 0.79v to 3.08v externally adjustable rstin threshold for auxiliary/triple-voltage monitoring (0.62v internal reference) watchdog timer option 35s (min) long startup period 1.12s (min) normal timeout period manual-reset input option power-fail input/power-fail output option (push-pull and open-drain active-low) guaranteed reset valid down to v cc 1 or v cc 2 = 0.8v reset output logic options immune to short v cc transients low supply current 14? (typ) at 3.6v watchdog disable feature small 5-, 6-, and 8-pin sot23 packages max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ maxim integrated products 1 ordering information in out2 out1 dc-dc converter unregulated dc r1 r2 v cc 1v cc 2 rstin/pfi mr rst wdi pfo max67_ _ pushbutton switch i/o supply core supply reset i/o nmi p 1.8v 0.9v max6715a- max6729a/ max6797a typical operating circuit 19-0536; rev 2; 6/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations and selector guide appear at end of data sheet. part temp range pin- package max6715a ut_ _d_+t -40? to +125? 6 sot23 max6716a ut_ _d_+t -40? to +125? 6 sot23 max6717a uk_ _d_+t -40? to +125? 5 sot23 max6718a uk_ _d_+t -40? to +125? 5 sot23 max6719a ut_ _d_+t -40? to +125? 6 sot23 max6720a ut_ _d_+t -40? to +125? 6 sot23 note: the first ? _?are placeholders for the threshold voltage levels of the devices. desired threshold levels are set by the part number suffix found in the reset voltage threshold suffix guide. the ??after the d is a placeholder for the reset timeout delay time. desired delay time is set using the timeout period suffix found in the reset timeout period suffix guide. for example, the max6716autltd3-t is a dual-voltage supervisor v th 1 = 4.625v, v th 2 = 3.075v, and 210ms (typ) timeout period. ordering information continued at end of data sheet. + denotes a lead-free/rohs-compliant package. t = tape and reel. multivoltage systems telecom/networking equipment computers/servers portable/battery- operated equipment industrial equipment printers/fax machines set-top boxes
max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits 2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ a a b b s s o o l l u u t t e e m m a a x x i i m m u u m m r r a a t t i i n n g g s s electrical characteristics (v cc 1 = 0.8v to 5.5v, v cc 2 = 0.8v to 5.5v, gnd = 0v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminal voltage (with respect to gnd) v cc 1, v cc 2 ..........................................................-0.3v to +6v open-drain rst , rst1 , rst2 , pfo , rst ................-0.3v to +6v push-pull rst, rst1 , pfo , rst ...............-0.3v to (v cc 1 + 0.3v) push-pull rst2 .........................................-0.3v to (v cc 2 + 0.3v) rstin, pfi, mr , wdi ................................................-0.3v to +6v input current/output current (all pins) ...............................20ma continuous power dissipation (t a = +70?) 5-pin sot23-5 (derate 7.1mw/? above +70?) ........571mw 6-pin sot23-6 (derate 8.7mw/? above +70?) ........696mw 8-pin sot23-8 (derate 8.9mw/? above +70?) ........714mw operating temperature range .........................-40? to +125? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply voltage v cc 0.8 5.5 v v cc 1 < 5.5v all i/o connections open, outputs not asserted 15 39 i cc1 v cc 1 < 3.6v all i/o connections open, outputs not asserted 10 28 v cc 2 < 3.6v all i/o connections open, outputs not asserted 411 supply current i cc2 v cc 2 < 2.75v all i/o connections open, outputs not asserted 39 ? l (falling) 4.500 4.625 4.750 m (falling) 4.250 4.375 4.500 t (falling) 3.000 3.075 3.150 s (falling) 2.850 2.925 3.000 r (falling) 2.550 2.625 2.700 z (falling) 2.250 2.313 2.375 y (falling) 2.125 2.188 2.250 w (falling) 1.620 1.665 1.710 v cc 1 reset threshold v th1 v (falling) 1.530 1.575 1.620 v t (falling) 3.000 3.075 3.150 s (falling) 2.850 2.925 3.000 r (falling) 2.550 2.625 2.700 z (falling) 2.250 2.313 2.375 y (falling) 2.125 2.188 2.250 w (falling) 1.620 1.665 1.710 v (falling) 1.530 1.575 1.620 i (falling) 1.350 1.388 1.425 h (falling) 1.275 1.313 1.350 g (falling) 1.080 1.110 1.140 f (falling) 1.020 1.050 1.080 e (falling) 0.810 0.833 0.855 v cc 2 reset threshold v th2 d (falling) 0.765 0.788 0.810 v max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 3 electrical characteristics (continued) (v cc 1 = 0.8v to 5.5v, v cc 2 = 0.8v to 5.5v, gnd = 0v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units reset threshold tempco v th /? 20 ppm/? reset threshold hysteresis v hyst referenced to v th typical 0.5 % v cc to reset output delay t rd v c c 1 = ( v th 1 + 100m v ) to ( v th 1 - 100m v ) or v c c 2 = ( v th 2 + 75m v ) to ( v th 2 - 75m v ) 20 ? d1 1.1 1.65 2.2 d2 8.8 13.2 17.6 d7 (max6797a only) 17.5 26.25 35 d8 (max6797a only) 35 52.5 70 d3 140 210 280 d5 280 420 560 d6 560 840 1120 reset timeout period t rp d4 1120 1680 2240 ms adjustable reset comparator input (max6719a/max6720a/max6723a?ax6727a) rstin input threshold v rstin 611 626.5 642 mv rstin input current i rstin -100 +100 na rstin hysteresis 3mv rstin to reset output delay t rstind v rstin to (v rstin - 30mv) 22 ? power-fail input (max6728a/max6729a) pfi input threshold v pfi 611 626.5 642 mv pfi input current i pfi -100 +100 na pfi hysteresis v pfh 3mv pfi to pfo delay t dpf (v pfi + 30mv) to (v pfi - 30mv) 2 s manual-reset input (max6715a?ax6722a/max6725a?ax6729a) v il 0.3 ? v cc 1 mr input voltage v ih 0.7 ? v cc 1 v mr minimum pulse width 1 s mr glitch rejection 100 ns mr to reset delay t mr 200 ns mr pullup resistance 25 50 80 k watchdog input (max6721a?ax6729a) first watchdog period after reset timeout period 35 54 72 watchdog timeout period t wd normal mode 1.12 1.68 2.24 s wdi pulse width t wdi (note 2) 50 ns v il 0.3 ? v cc 1 wdi input voltage v ih 0.7 ? v cc 1 v wdi input current i wdi wdi = 0v or v cc 1-1+1 a max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits 4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ note 1: devices tested at t a = +25?. overtemperature limits are guaranteed by design and not production tested. note 2: parameter guaranteed by design. electrical characteristics (continued) (v cc 1 = 0.8v to 5.5v, v cc 2 = 0.8v to 5.5v, gnd = 0v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units reset/power-fail outputs v cc 1 or v cc 2 0.8v, i sink = 1?, output asserted 0.3 v cc 1 or v cc 2 1.0v, i sink = 50?, output asserted 0.3 v cc 1 or v cc 2 1.2v, i sink = 100?, output asserted 0.3 v cc 1 or v cc 2 2.7v, i sink = 1.2ma, output asserted 0.3 rst / rst1 / rst2 / pfo output low (push-pull or open-drain) v ol v cc 1 or v cc 2 4.5v, i sink = 3.2ma, output asserted 0.4 v v cc 1 1.8v, i source = 200?, output not asserted 0.8 ? v cc 1 v cc 1 2.7v, i source = 500?, output not asserted 0.8 ? v cc 1 rst / rst1 / pfo output high (push-pull only) v oh v cc 1 4.5v, i source = 800?, output not asserted 0.8 ? v cc 1 v v cc 1 1.8v, i source = 200?, output not asserted 0.8 ? v cc 2 v cc 1 2.7v, i source = 500?, output not asserted 0.8 ? v cc 2 rst2 output high (push-pull only) v oh v cc 1 4.5v, i source = 800?, output not asserted 0.8 ? v cc 2 v v cc 1 1.0v, i source = 1?, reset asserted 0.8 ? v cc 1 v cc 1 1.8v, i source = 150?, reset asserted 0.8 ? v cc 1 v cc 1 2.7v, i source = 500?, reset asserted 0.8 ? v cc 1 rst output high (push-pull only) v oh v cc 1 4.5v, i source = 800?, reset asserted 0.8 ? v cc 1 v v cc 1 or v cc 2 1.8v, i sink = 500?, reset not asserted 0.3 v cc 1 or v cc 2 2.7v, i sink = 1.2ma, reset not asserted 0.3 rst output low (push-pull or open drain) v ol v cc 1 or v cc 2 4.5v, i sink = 3.2ma, reset not asserted 0.4 v rst / rst1 / rst2 / pfo output open-drain leakage current output not asserted 0.5 ? rst output open-drain leakage current output asserted 0.5 ? max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _______________________________________________________________________________________ 5 0 2 6 4 12 10 8 18 16 14 20 -40 20 -10 50 80 5 -25 35 65 110 95 125 supply current vs. temperature (v cc 1 = +5v, v cc 2 = +3.3v) max6715a-29a toc01 temperature ( c) supply current ( a) total i cc 1 i cc 2 0 4 2 10 8 6 18 16 14 12 20 supply current vs. temperature (v cc 1 = +3.3v, v cc 2 = +2.5v) max6715a-29a toc02 temperature ( c) supply current ( a) -40 20 -10 50 80 5 -25 35 65 110 95 125 total i cc 1 i cc 2 0 2 6 4 12 10 8 18 16 14 20 -40 20 -10 50 80 5 -25 35 65 110 95 125 supply current vs. temperature (v cc 1 = +2.5v, v cc 2 = +1.8v) max6715a-29a toc03 temperature ( c) supply current ( a) total i cc 1 i cc 2 0 2 6 4 12 10 8 18 16 14 20 -40 20 -10 50 80 5 -25 35 65 110 95 125 supply current vs. temperature (v cc 1 = +1.8v, v cc 2 = +1.2v) max6715a-29a toc04 temperature ( c) supply current ( a) total i cc 1 i cc 2 0.980 0.984 0.992 0.988 1.004 1.000 0.996 1.016 1.012 1.008 1.020 -40 20 -10 50 80 5 -25 35 65 110 95 125 normalized/reset watchdog timeout period vs. temperature max6715a-29a toc05 temperature ( c) reset/watchdog timeout period 10,000 1000 100 10 1100 10 1000 maximum v cc transient duration vs. reset threshold overdrive max6715a-29a toc06 reset threshold overdrive (mv) maximum v cc transient duration ( s) reset occurs above this line 0.998 0.999 1.001 1.000 1.004 1.003 1.002 1.007 1.006 1.005 1.008 -40 20 -10 50 80 5 -25 35 65 110 95 125 normalized v cc reset threshold vs. temperature max6715a-29a toc07 temperature ( c) reset threshold 628 630 629 633 632 631 637 636 634 635 638 -40 20 -10 50 80 5 -25 35 65 110 95 125 reset input and power-fail input threshold vs. temperature max6715a-29a toc08 temperature ( c) reset threshold 10 11 13 12 16 15 14 19 18 17 20 -40 20 -10 50 80 5 -25 35 65 110 95 125 v cc to reset delay vs. temperature max6715a-29a toc09 temperature ( c) v cc to reset delay ( s) 75mv overdrive typical operating characteristics (v cc 1 = 5v, v cc 2 = 3.3v, t a = +25?, unless otherwise noted.) max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits 6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ pin description 12 16 14 22 20 18 24 -40 20 -10 50 80 5 -25 35 65 110 95 125 rstin input to reset output delay vs. temperature max6715a-29a toc10 temperature ( c) rstin to reset delay ( s) 30mv overdrive 1.0 1.2 1.8 1.6 1.4 1.3 1.1 1.9 1.7 1.5 2.0 -40 20 -10 50 80 5 -25 35 65 110 95 125 power-fail input to power-fail output delay vs. temperature max6715a-29a toc11 temperature ( c) power-fail delay ( s) 30mv overdrive 0v 0v v rst 2v/div max6715a-29a toc12 50ns/div mr to reset output delay v mr 2v/div typical operating characteristics (continued) (v cc 1 = 5v, v cc 2 = 3.3v, t a = +25?, unless otherwise noted.) pin m ax6 7 1 5a/ m ax6 7 1 6a m ax6 7 1 7a/ m ax6 7 1 8a m ax6 7 1 9a/ m ax6 7 2 0a m ax6 7 2 1a/ m ax6 7 2 2a m ax6 7 2 3a/ m ax6 7 2 4a m ax6 7 2 5a/ m ax6 7 2 6a m ax6 7 2 7a m ax6 7 2 8a/ m ax6 7 2 9a/ m ax6 7 9 7a name function 1 1 1 1 1 1 1, 4 1 rst / rst1 active-low reset output, open-drain or push-pull. rst/rst1 changes from high to low when v cc 1 or v cc 2 drops below the selected reset thresholds, rstin is below threshold, mr is pulled low, or the watchdog triggers a reset. rst/rst1 remains low for the reset timeout period after v cc 1/ v cc 2/rstin exceed the device reset thresholds, mr goes low to high, or the watchdog triggers a reset. open- drain outputs require an external pullup resistor. push-pull outputs are referenced to v cc 1. max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 7 pin description (continued) pin max6715a/ max6716a max6717a/ max6718a max6719a / max6720a max6721a/ max6722a max6723a / max6724a max6725a/ max6726a max6727a m ax6 7 2 8a/ m ax6 7 2 9a/ m ax6 7 9 7a name function 5 rst2 active-low reset output, open-drain or push-pull. rst2 changes from high to low when v cc 1 or v cc 2 drops below the selected reset thresholds or mr is pulled low. rst2 remains low for the reset timeout period after v cc 1/v cc 2 exceed the device reset thresholds or mr goes low to high. open-drain outputs r eq ui r e an exter nal p ul l up r esi stor . p ush- p ul l outp uts are referenced to v cc 2. 2 2 2 2 2 2 2 2 gnd ground 3333 555 mr active-low manual-reset input. internal 50k pullup to v cc 1. pull low to force a reset. reset remains active as long as mr is low and for the reset timeout period after mr goes high. leave unconnected or connect to v cc 1 if unused. 4 44 4 4666v cc 2 secondary supply voltage input. powers the device when it is above v cc 1 and input for secondary reset threshold monitor. 6 56 6 6888v cc 1 primary supply voltage input. powers the device when it is above v cc 2 and input for primary reset threshold monitor. max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits 8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ pin description (continued) pi n m ax6 7 1 5a/ m ax6 7 1 6a m ax6 7 1 7a/ m ax6 7 1 8a m ax6 7 1 9a/ m ax6 7 2 0a m ax6 7 2 1a/ m ax6 7 2 2a m ax6 7 2 3a/ m ax6 7 2 4a m ax6 7 2 5a/ m ax6 7 2 6a m ax6 7 2 7a m ax6 7 2 8a/ m ax6 7 2 9a/ m ax6 7 9 7a name function ? 3333wdi watchdog input. if wdi remains high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and the reset output asserts for the reset timeout period. the internal watchdog timer clears whenever a reset is asserted or wdi sees a rising or falling edge. the watchdog has a long startup period (35s min) after each reset event and a short watchdog timeout period (1.12s min) after the first valid wdi transition. leave wdi unconnected to disable the watchdog timer. the wdi unconnected-state detector uses a small 200na current source. therefore, do not connect wdi to anything that will source more than 50na. 5 5 7 7 rstin undervoltage reset comparator input. high- impedance input for adjustable reset monitor. the reset output is asserted when rstin falls below the 0.626v internal reference voltage. set the monitored voltage reset threshold with an external resistor-divider network. connect rstin to v cc 1 or v cc 2 if not used. max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 9 pin description (continued) pin m a x6 7 1 5a / m a x6 7 1 6a m a x6 7 1 7a / m a x6 7 1 8a m a x6 7 1 9a / m a x6 7 2 0a m a x6 7 2 1a / m a x6 7 2 2a m a x6 7 2 3a / m a x6 7 2 4a m a x6 7 2 5a / m a x6 7 2 6a m a x6 7 2 7a m ax6 7 2 8a/ m ax6 7 2 9a/ m ax6 7 9 7a name function ?pfi power-fail voltage monitor input. high- impedance input for internal power-fail monitor comparator. connect pfi to an external resistor- divider network to set the power-fail threshold voltage (0.626v typical internal reference voltage). connect to gnd, v cc 1, or v cc 2 if not used. ? pfo active-low power-fail monitor output, open- drain or push-pull. pfo is asserted low when pfi is less than 0.626v. pfo deasserts without a reset timeout period. open- drain outputs require an external pullup resistor. push-pull outputs are referenced to v cc 1. 4 rst active-high reset output, open-drain or push-pull. rst changes from low to high when v cc 1 or v cc 2 drops below selected reset thresholds, rstin is below threshold, mr is pulled low, or the watchdog triggers a reset. rst remains high for the reset timeout period after v cc 1/v cc 2/rstin exceed the device reset thresholds, mr goes low to high, or the watchdog triggers a reset. open- drain outputs require an external pullup resistor. push-pull outputs are referenced to v cc 1. detailed description supply voltages the max6715a?ax6729a/max6797a ? supervisory circuits maintain system integrity by alerting the ? to fault conditions. these ics are optimized for systems that monitor two or three supply voltages. the output- reset state is guaranteed to remain valid while either v cc 1 or v cc 2 is above 0.8v. threshold levels input-voltage threshold level combinations are indicat- ed by a two-letter code in the reset voltage threshold suffix guide (table 1). contact factory for availability of other voltage threshold combinations. reset outputs the max6715a?ax6729a/max6797a provide an active-low reset output ( rst ) and the max6725a/ max6726a also provide an active-high (rst) output. rst, rst , rst1 , and rst2 are asserted when the volt- age at either v cc 1 or v cc 2 falls below the voltage threshold level, rstin drops below threshold, or mr is pulled low. once reset is asserted, it stays low for the reset timeout period (see table 2). if v cc 1, v cc 2, or rstin goes below the reset threshold before the reset timeout period is completed, the internal timer restarts. the max6715a/max6717a/max6719a/max6721a/ max6723a/max6725a/max6727a/max6728a contain open-drain reset outputs, while the max6716a/ max6718a/max6720a/max6722a/max6724a/ max6726a/max6729a/max6797a contain push-pull reset outputs. the max6727a provides two separate open-drain rst outputs driven by the same internal logic. manual-reset input many ?-based products require manual-reset capabil- ity, allowing the operator, a test technician, or external logic circuitry to initiate a reset. a logic-low on mr asserts the reset output. reset remains asserted while mr is low for the reset timeout period (t rp ) after mr returns high. this input has an internal 50k pullup resistor to v cc 1 and can be left unconnected if not used. mr can be driven with cmos logic levels, or with open-drain/collector outputs. connect a normally open momentary switch from mr to gnd to create a manual- reset function; external debounce circuitry is not required. if mr is driven from long cables or if the device is used in a noisy environment, connect a 0.1? capacitor from mr to gnd to provide additional noise immunity. adjustable input voltage the max6719a/max6720a and max6723a?ax6727a provide an additional input to monitor a third system volt- age. the threshold voltage at rstin is typically 626mv. connect a resistor-divider network to the circuit as shown in figure 1 to establish an externally controlled threshold voltage, v ext_th . v ext_th = 626mv((r1 + r2)/r2) low-leakage current at rstin allows the use of large- valued resistors resulting in reduced power consump- tion of the system. watchdog input the watchdog monitors ? activity through the watch- dog input (wdi). to use the watchdog function, con- nect wdi to a bus line or ? i/o line. when wdi remains high or low for longer than the watchdog time- out period, the reset output asserts. the max6721a?ax6729a/max6797a include a dual- mode watchdog timer to monitor ? activity. the flexi- ble timeout architecture provides a long period initial watchdog mode, allowing complicated systems to complete lengthy boots, and a short period normal watchdog mode, allowing the supervisor to provide quick alerts when processor activity fails. after each reset event (v cc power-up/brownout, manual reset, or watchdog reset), there is a long initial watchdog period of 35s minimum. the long watchdog period mode pro- vides an extended time for the system to power-up and fully initialize all ? and system components before assuming responsibility for routine watchdog updates. max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits 10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ max6719a/ max6720a/ max6723a max6727a v ext_th r1 r2 rstin gnd figure 1. monitoring a third voltage max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 11 the normal watchdog timeout period (1.12s min) begins after the first transition on wdi before the con- clusion of the long initial watchdog period (figure 2). during the normal operating mode, the supervisor will issue a reset pulse for the reset timeout period if the ? does not update the wdi with a valid transition (high-to- low or low-to-high) within the standard timeout period (1.12s min). leave wdi unconnected to disable the watchdog timer. the wdi unconnected-state detector uses a small (200na typ) current source. therefore, do not connect wdi to anything that will source more than 50na. power-fail comparator pfi is the noninverting input to a comparator. if pfi is less than v pfi (626.5mv), pfo goes low. common uses for the power-fail comparator include monitoring prereg- ulated input of the power supply (such as a battery) or providing an early power-fail warning so software can conduct an orderly system shutdown. it can also be used to monitor supplies other than v cc 1 or v cc 2 by setting the power-fail threshold with a resistor-divider, as shown in figure 3. pfi is the input to the power-fail com- parator. the typical comparator delay is 2? from pfi to pfo . connect pfi to ground of v cc 1 if unused. ensuring a valid reset output down to v cc = 0v the max6715a?ax6729a/max6797a are guaranteed to operate properly down to v cc = 0.8v. in applications that require valid reset levels down to v cc = 0v, use a pulldown resistor at rst to ground. the resistor value used is not critical, but it must be large enough not to load the reset output when v cc is above the reset thresh- old. for most applications, 100k is adequate. this con- figuration does not work for the open-drain outputs of the max6715a/max6717a/max6719a/max6721a/ max6723a/max6725a/max6727a/max6728a. for push- pull, active-high rst output connect the external resistor as a pullup from rst to v cc 1. 1.12s max t wdi-normal 1.12s max t wdi-startup 35s max v th v cc wdi rst t rp figure 2. normal watchdog startup sequence max6728a/ max6729a/ max6797a r1 r2 pfi gnd v in pfo v trip = v pfi r1 + r2 r2 () max6728a/ max6729a/ max6797a r1 r2 pfi gnd v cc v in pfo v trip = r2 (v pfi ) 1 r1 1 r2 +- v cc r1 [] () v pfi = 626.5mv a) b) figure 3. using power-fail input to monitor an additional power-supply a) v in is positive b) v in is negative max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits 12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ max6729a v ext r1 r3 r2 pfi gnd pfo a v good = desired v ext good voltage threshold v fail = desired v ext fail voltage threshold v oh = v cc 1 (for push-pull pfo) r2 = 50k (for > 10 a r2 current) r1 = r2 ((v good - v pfi ) - (v pfi )(v good - v fail )/v oh )/v pfi r3 = (r1 x v oh )/(v good - v fail ) v good v fail v in pfo figure 5. adding hysteresis to power-fail for push-pull pfo applications information interfacing to ?s with bidirectional reset pins most ?s with bidirectional reset pins can interface directly to open-drain rst output options. systems simultaneously requiring a push-pull rst output and a bidirectional reset interface can be in logic contention. to prevent contention, connect a 4.7k resistor between rst and the ?? reset i/o port as shown in figure 4. adding hysteresis to the power-fail comparator the power-fail comparator has a typical input hysteresis of 3mv. this is sufficient for most applications where a power-supply line is being monitored through an external voltage-divider (see the power-fail comparator section). if additional noise margin is desired, connect a resistor between pfo and pfi as shown in figure 5. select the values of r1, r2, and r3 so pfi sees v pfi (626mv) when v ext falls to its power-fail trip point (v fail ) and when v in rises to its power-good trip point (v good ). the hysteresis window extends between the specified v fail and v good thresholds. r3 adds the additional hysteresis by sinking current from the r1/r2 divider network when pfo is logic-low and sourcing current into the network when pfo is logic-high. r3 is typically an order of magnitude greater than r1 or r2. the current through r2 should be at least 2.5? to ensure that the 100na (max) pfi input current does not signifi- cantly shift the trip points. therefore, r2 < v pfi /10? < 62k for most applications. r3 will provide additional hys- teresis for pfo push-pull (v oh = v cc 1) or open-drain (v oh = v pullup ) applications. monitoring an additional power supply these ? supervisors can monitor either positive or negative supplies using a resistor voltage-divider to pfi. pfo can be used to generate an interrupt to the ? or cause reset to assert (figure 3). monitoring a negative voltage the power-fail comparator can be used to monitor a negative supply voltage using the circuit shown in figure 3. when the negative supply is valid, pfo is low. when the negative supply voltage drops, pfo goes high. the circuit? accuracy is affected by the pfi threshold tolerance, v cc , r1, and r2. negative-going v cc transients the max6715a?ax6729a/max6797a supervisors are relatively immune to short-duration negative-going v cc transients (glitches). it is usually undesirable to reset the ? when v cc experiences only small glitches. the typical operating characteristics show maximum transient duration vs. reset threshold overdrive, for which reset pulses are not generated. the graph was produced using negative-going v cc pulses, starting above v th and ending below the reset threshold by the max6715a max6729a/ max6797a gnd gnd v cc 1v cc 2 v cc 2 v cc 1 rst reset to other system components reset p 4.7k figure 4. interfacing to ?s with bidirectional reset i/o max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 13 magnitude indicated (reset threshold overdrive). the graph shows the maximum pulse width that a negative- going v cc transient may typically have without causing a reset pulse to be issued. as the amplitude of the tran- sient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. a 0.1? bypass capacitor mounted close to the v cc pin provides additional transient immunity. watchdog software considerations setting and resetting the watchdog input at different points in the program, rather than ?ulsing?the watch- dog input high-low-high or low-high-low, helps the watchdog timer to closely monitor software execution. this technique avoids a ?tuck?loop where the watch- dog timer continues to be reset within the loop, keeping the watchdog from timing out. figure 6 shows an exam- ple flow diagram where the i/o driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. if the program should ?ang?in any subroutine, the i/o is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. start set wdi high program code subroutine or program loop set wdi low return subroutine completed hang in subroutine figure 6. watchdog flow diagram max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits 14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ functional diagram v cc 1 v ref v cc 2 rstin/pfi v ref v cc 1 mr v cc 1 v cc 1 v cc 1 reset timeout period v cc 2 rst rst pfo watchdog timer wdi v cc 1 mr pullup reset output driver v ref/2 max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 15 selector guide part number of voltage monitors open- drain reset open- drain reset push- pull reset push- pull reset manual reset watch- dog input power- fail input/ output max6715a 2 2 max6716a 2 2 max6717a 2 1 max6718a 2 1 max6719a 3 1 max6720a 3 1 max6721a 2 1 ? max6722a 2 1 ? max6723a 3 1 max6724a 3 1 max6725a 3 1 1 ? max6726a 3 1 1 ? max6727a 3 2 ? max6728a 3 1 ?? (open drain) max6729a 3 1 ?? (push-pull) max6797a 3 1 ?? (open drain) ordering information (continued) part temp range pin- package max6721a ut_ _d_+t -40? to +125? 6 sot23 max6722a ut_ _d_+t -40? to +125? 6 sot23 max6723a ut_ _d_+t -40? to +125? 6 sot23 max6724a ut_ _d_+t -40? to +125? 6 sot23 max6725a ka_ _d_+t -40? to +125? 8 sot23 max6726a ka_ _d_+t -40? to +125? 8 sot23 max6727a ka_ _d_+t -40? to +125? 8 sot23 max6728a ka_ _d_+t -40? to +125? 8 sot23 max6729a ka_ _d_+t -40? to +125? 8 sot23 max6797a ka_ _d_+t -40? to +125? 8 sot23 note: the first ? _?are placeholders for the threshold voltage levels of the devices. desired threshold levels are set by the part number suffix found in the reset voltage threshold suffix guide. the ??after the d is a placeholder for the reset timeout delay time. desired delay time is set using the timeout period suffix found in the reset timeout period suffix guide. for example, the max6716autltd3-t is a dual-voltage supervisor v th 1 = 4.625v, v th 2 = 3.075v, and 210ms (typ) timeout period. + denotes a lead-free/rohs-compliant package. t = tape and reel. max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits 16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ table 1. reset voltage threshold suffix guide** part number suffix (_ _) v cc 1 nominal voltage threshold (v) v cc 2 nominal voltage threshold (v) lt 4.625 3.075 ms 4.375 2.925 mr 4.375 2.625 tz 3.075 2.313 sy 2.925 2.188 ry 2.625 2.188 tw 3.075 1.665 sv 2.925 1.575 rv 2.625 1.575 ti 3.075 1.388 sh 2.925 1.313 rh 2.625 1.313 tg 3.075 1.110 sf 2.925 1.050 rf 2.625 1.050 te 3.075 0.833 sd 2.925 0.788 rd 2.625 0.788 zw 2.313 1.665 yv 2.188 1.575 zi 2.313 1.388 yh 2.188 1.313 zg 2.313 1.110 yf 2.188 1.050 ze 2.313 0.833 yd 2.188 0.788 wi 1.665 1.388 vh 1.575 1.313 wg 1.665 1.110 vf 1.575 1.050 we 1.665 0.833 vd 1.575 0.788 table 2. reset timeout period suffix guide active timeout period timeout period suffix min (ms) max (ms) d1 1.1 2.2 d2 8.8 17.6 d7 ? 17.5 35.0 d8 ? 35.0 70.0 d3 140 280 d5 280 560 d6 560 1120 d4 1120 2240 ** standard versions are shown in bold and are available in a d3 timeout option only. standard versions require 2,500 piece order increments and are typically held in sample stock. there is a 10,000 order increment on nonstandard versions. other thresh- old voltages may be available, contact factory for availability. ? d7 and d8 timeout periods are only available for the max6797a. max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 17 pin configurations gnd v cc 2 16 v cc 1 5 max6715a/ max6716a sot23 top view 2 34 rst1 mr rst2 gnd v cc 2 16 v cc 1 5 max6721a/ max6722a sot23 2 34 rst mr wdi gnd v cc 2 16 v cc 1 5 max6723a/ max6724a sot23 2 34 rst wdi rstin 5 rstin gnd v cc 2 15 v cc 1 max6717a/ max6718a sot23 2 34 rst mr gnd v cc 2 16 v cc 1 max6719a/ max6720a sot23 2 34 rst mr v cc 2 mr rst 1 2 8 7 v cc 1 rstin gnd wdi rst sot23 3 4 6 5 max6725a/ max6726a v cc 2 mr 1 2 8 7 v cc 1 rstin gnd wdi rst sot23 3 4 6 5 max6727a rst v cc 2 mr 1 2 8 7 v cc 1 pfi gnd wdi rst sot23 3 4 6 5 max6728a/ max6729a/ max6797a pfo chip information transistor count: 1072 process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 5 sot23 u5-1 21-0057 6 sot23 u6-1 21-0058 8 sot23 k8sn-1 21-0078 max6715a?ax6729a/max6797a dual/triple, ultra-low-voltage, sot23 ? supervisory circuits maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. heaney revision history revision number revision date description pages changed 0 4/06 initial release 1 7/06 updated ordering information . 1, 15 2 6/08 added the max6797a to ordering information , electrical characteristics , pin description , detailed description , figures 4 and 5, selector guide , table 2, pin configurations . 1, 2, 6?1, 12, 15?7 |
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